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19-1734; Rev 0; 5/00
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
General Description
The MAX5264 contains eight 14-bit, voltage-output digital-to-analog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The device operates from +14V/-9V supplies. Its bipolar output voltage swing ranges from +9V to -4V and is achieved with no external components. The MAX5264 has three pairs of differential reference inputs; two of these pairs are connected to two DACs each, and a third pair is connected to four DACs. The references are independently controlled, providing different full-scale output voltages to the respective DACs. The MAX5264 operates within the following voltage ranges: VDD = +7V to +14V, VSS = -5V to -9V, and VCC = +4.75V to +5.25V. The MAX5264 features double-buffered interface logic with a 14-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (LD) transfers data from the input latch to the DAC latch. The LD input controls all DACs; therefore, all DACs can be updated simultaneously by asserting the LD pin. An asynchronous CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The "A" grade of the MAX5264 has a MAXIMum INL of 4LSBs, while the "B" grade has a MAXIMum INL of 8LSBs. Both grades are available in 44-pin MQFP packages. o 8 DACs in a Single Package o Buffered Voltage Outputs o Unipolar or Bipolar Voltage Swing to +9V and -4V o 22s Output Settling Time o Drives Up to 10,000pF Capacitive Load o Low Output Glitch: 30mV o Low Power Consumption: 10mA (typ) o Small 44-Pin MQFP Package o Double-Buffered Digital Inputs o Asynchronous Load Updates All DACs Simultaneously o Asynchronous CLR Forces All DACs to DUTGND Potential
Features
o Full 14-Bit Performance Without Adjustments
MAX5264
Ordering Information
PART MAX5264ACMH MAX5264BCMH TEMP. RANGE 0C to +70C 0C to +70C PINPACKAGE 44 MQFP 44 MQFP INL (LSB) 4 8
Pin Configuration
TOP VIEW
OUTB OUTC DUTGNDCD OUTD REFCDEFREFCDEF+ VDD OUTE DUTGNDEF OUTF OUTG
44 43 42 41 40 39 38 37 36 35 34
Applications
Automatic Test Equipment (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment Minimum Component Count Analog Systems Digital Offset/Gain Adjustment SONET Applications
DUTGNDAB OUTA REFABREFAB+ VDD VSS LD A2 A1 A0 CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
DUTGNDGH OUTH REFGHREFGH+ CLR D13 D12 D11 D10 D9 D8
MAX5264
Functional Diagram appears at end of data sheet.
________________________________________________________________ MAXIM Integrated Products
WR VCC GND D0 D1 D2 D3 D4 D5 D6 D7
MQFP
1
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
ABSOLUTE MAXIMUM RATINGS
VDD to GND ........................................................-0.3V to +16.8V VSS to GND ........................................................ -10.8V to +0.3V VCC to GND ............................................................ -0.3V to +6V A_, D_, WR, CS, LD, CLR to GND.............+0.3V to (VCC + 0.3V) REF_ _ _ _+, REF_ _ _ _-, DUTGND_ _ ..................................(VSS - 0.3V) to (VDD + 0.3V) OUT_ ..........................................................................VDD to VSS MAXIMum Current into REF_ _ _ _ _, DUTGND_ _ ...........10mA MAXIMum Current into Any Signal Pin ..............................50mA OUT_ Short-Circuit Duration to VDD, VSS, and GND ................1s Continuous Power Dissipation (TA = +70C) 44-Pin MQFP (derate 11.1mW/C above +70C)..........870mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute MAXIMum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute MAXIMum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk REFERENCE INPUTS Input Resistance Input Current REF_ _ _ _+ Input Range REF_ _ _ _- Input Range (REF_ _ _ _+) - (REF_ _ _ _-) Range VDD - (2 * VREF_ _ _ _ +) Range (2 * VREF_ _ _ _-) - VSS Range VDD - (VREF_ _ _ _ +) Range (VREF_ _ _ _-) - VSS Range ANALOG OUTPUTS MAXIMum Output Voltage Minimum Output Voltage Resistive Load to GND Capacitive Load to GND DC Output Impedance (Note 2) (Note 1) 5 10,000 0.5 9 VDD - 2 VSS + 2 -4 V V k pF 1.5 -2.0 3 3.5 3.5 7.5 5 1 1 10 4.5 -1.5 6.5 8.5 5 10 7 M A V V V V V V V (Note 1) (Note 1) SYMBOL N INL DNL MAX5264A MAX5264B Guaranteed monotonic 4 8 4 0.15 14 CONDITIONS MIN 14 4 8 1 8 16 10 20 75 TYP MAX UNITS Bits LSB LSB LSB LSB LSB ppm FSR/C V STATIC PERFORMANCE (ANALOG SECTION)
2
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Impedance per DAC Input Current per DAC Input Range DIGITAL INPUTS Input Voltage High Input Voltage Low Input Capacitance Input Current POWER SUPPLIES VDD Analog Power-Supply Range VSS Analog Power-Supply Range VDD - VSS Digital Power Supply Positive Supply Current Negative Supply Current Digital Supply Current PSRR, VOUT / VDD PSRR, VOUT / VSS VCC IDD ISS ICC RL = 10k, VOUT_ = 9V (Note 3) RL = 10k, VOUT_ = -4 (Note 4) (Note 5) (Note 6) VDD = 14V 5% VSS = -9V 5% 94 98 VDD VSS 11.5 -9 18 4.75 5 14 -6.5 23 5.25 20 20 0.5 5 V V V V mA mA mA dB dB VIH VIL CIN IIN (Note 1) VIN = 0 or VCC -1 2.4 0.8 10 1 V V pF A (Note 1) SYMBOL CONDITIONS MIN 55 -120 -2 TYP 115 73 2 MAX UNITS k A V DUTGND_ _ CHARACTERISTICS
MAX5264
INTERFACE TIMING CHARACTERISTICS
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, Figure 2, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CS Pulse Width Low WR Pulse Width Low LD Pulse Width Low CS Low to WR Low CS High to WR High Data Valid to WR Setup Data Valid to WR Hold Address Valid to WR Setup Address Valid to WR Hold SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 CONDITIONS MIN 50 50 50 0 0 50 0 15 0 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
DYNAMIC CHARACTERISTICS
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Output Settling Time Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Channel-to-Channel Isolation Output Noise Spectral Density Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: At = 1kHz (Note 7) (Note 8) SYMBOL CONDITIONS To 1LSB of full scale MIN TYP 22 1 3 3 120 3 100 130 MAX UNITS s V/s nVs nVs nVs nVs dB nV/Hz
Guaranteed by design. Not production tested. Guaranteed by design when 220 resistor is in series with CL = 10,000pF. All DAC latches at full scale (0x3FFF). All DAC latches at zero scale (0x0000). All digital inputs (D_, A_, WR, CS, LD, and CLR) at GND or VCC potential. All digital inputs (D_, A_, WR, CS, LD, and CLR) at +0.8V or +2.4V. All data inputs (D0 to D13) transition from GND to VCC, with WR = VCC. All digital inputs (D_, A_, WR, CS, LD, and CLR) at +0.8V or +2.4V.
Typical Operating Characteristics
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX5264-01
DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
MAX5264-02
INL AND DNL ERROR vs. TEMPERATURE
MAX5264-03
0.4 0.3 0.2 INL (LSB)
0.4 0.3 0.2
0.4
0.3 ERROR (LSB)
INL
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 0 4000 8000 12,000 16,000 DIGITAL CODE
0.1 0 -0.1 -0.2 -0.3 -0.4 0 4000 8000 12,000 16,000 DIGITAL CODE
0.2 DNL 0.1
0 0 10 20 30 40 50 60 70 TEMPERATURE (C)
4
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
Typical Operating Characteristics (continued)
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25C, unless otherwise noted.)
ZERO-SCALE AND FULL-SCALE ERROR vs. TEMPERATURE
MAX5264-04
MAX5264
IDD AND ISS vs. TEMPERATURE (WITH 10k LOADS)
15 14 IDD, ISS (mA) IDD
MAX5264-05
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX5264-06
0.4 0.3 0.2 ERROR (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 10 20 30 40 50 60 FULL SCALE ZERO SCALE
16
30 28 26 ICC (A) 24 22 20
13 12 11 10 9 8 ISS
18 16 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 TEMPERATURE (C) TEMPERATURE (C)
70
TEMPERATURE (C)
REFERENCE INPUT FREQUENCY RESPONSE
MAX5264-07
SETTLING TIME vs. CAPACITIVE LOAD
MAX5264-08
LARGE-SIGNAL STEP RESPONSE
MAX5264-09
5 0 -5 AMPLITUDE (dB) -10 -15 -20 -25 -30 -35 -40 1k 10k 100k
100 90 80 SETTLING TIME (S) 70 60 50 40 30 20 10 0
REF_ _ = 200 mVp-p
DATA D13-D0 5V/div OUT 5V/div
1M
10M
10
100
1000
10,000
100,000
5s/div
FREQUENCY (Hz)
CAPACITIVE LOAD (pF)
POSITIVE SETTLING TIME
MAX5264-10
NEGATIVE SETTLING TIME
MAX5264-11
NOISE VOLTAGE DENSITY vs. FREQUENCY
MAX5264-12
1000 NOISE VOLTAGE DENSITY (nV/Hz) 100 10
LD 5V/div
LD 5V/div
OUT 1mV/div
OUT 1mV/div
5s/div
5s/div
100
1k
10k
FREQUENCY (Hz)
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Typical Operating Characteristics (continued)
(VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25C, unless otherwise noted.)
MAJOR CARRY GLITCH IMPULSE (0 x 1FFF - 0 x 2000)
MAX5264-13
MAJOR CARRY GLITCH IMPULSE (0 x 2000 - 0 x 1FFF)
MAX5264-14
GAIN ERROR vs. VREF (VREF+ - VREF-)
1.0 0.8 GAIN ERROR (LSB) 0.6 0.4 0.2 0 -0.2 D -0.4 B C E 8 10 A SEE TABLE 1
MAX5264-15
1.2
LD 5V/div
LD 5V/div
OUT 5mV/div
OUT 5mV/div
2s/div
2s/div
0
2
4 VREF (V)
6
DNL (MAX, MIN) vs. VREF (VREF+ - VREF-)
MAX5264-16
Z.S.E. vs. VREF (VREF+ - VREF-)
A 1.2 1.0 Z.S.E. (LSB) 0.8 C 0.6 0.4 D B E SEE TABLE 1
MAX5264-17
0.4 0.3 DNL (MAX, MIN) (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 2 4 VREF (V) 6 A B C A B C
1.4
SEE TABLE 1 D E
D
E
0.2 0
8
10
0
2
4 VREF (V)
6
8
10
F.S.E. vs. VREF (VREF+ - VREF-)
MAX5264-18
INL (MAX, MIN) vs. VREF (VREF+ - VREF-)
0.4 INL (MAX, MIN) (LSB) 0.3 0.2 0.1 0 -0.1 D E -0.2 -0.3 0 2 4 VREF (V) 6 8 10 10 A B C D E A B C D E SEE TABLE 1
MAX5264-19
0.8 0.7 0.6 F.S.E. (LSB) 0.5 0.4 0.3 0.2 0.1 0 0 2 4 VREF (V) 6 C B A
SEE TABLE 1
0.5
8
6
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Table 1. Test Conditions for Static Performance Typical Operating Characteristics
VOLTAGE VREF VREF+ VREFVDD VSS Note: VREF = VREF+ - VREFA 2 1 -1 7 -5 B 4 2.25 -1.75 7 -5.5 C 6.5 4.5 -2 11 -6 D 8 5 -3 12 -8 E 9.5 6 -3.5 14 -9
Pin Description
PIN 1 2 3 4 5, 38 6 7 8 9 10 11 12 NAME DUTGNDAB OUTA REFABREFAB+ VDD VSS LD A2 A1 A0 CS WR FUNCTION Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB. DAC A Buffered Output Voltage Negative Reference Input for DACs A and B Positive Reference Input for DACs A and B Positive Analog Power Supply. Normally set to +14V. Connect both pins to the supply voltage. See Grounding and Bypassing section for bypass requirements. Negative Analog Power Supply. Normally set to -9V. See Power Supplies, Grounding, and Bypassing section for bypass requirements. Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their respective DAC latches. DAC latches are transparent when LD is low and latched when LD is high. Address Bit 2 (MSB) Address Bit 1 Address Bit 0 (LSB) Chip Select. Active-low input. Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transparent when WR and CS are both low. WR latches data into the DAC input latch selected by A2-A0 on the rising edge of CS. Digital Power Supply. Normally set to +5V. See Power Supplies, Grounding, and Bypassing section for bypass requirements. Ground Data Bits 0-13. Offset binary coding. Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _. Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes high. Positive Reference Input for DACs G and H Negative Reference Input for DACs G and H
13 14 15-28 29 30 31
VCC GND D0-D13 CLR REFGH+ REFGH-
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Pin Description (continued)
PIN 32 33 34 35 36 37 39 40 41 42 43 44 NAME OUTH DUTGNDGH OUTG OUTF DUTGNDEF OUTE REFCDEF+ REFCDEFOUTD DUTGNDCD OUTC OUTB DAC H Buffered Output Voltage Device Sense Ground Input for OUTG and OUTH. In normal operation, OUTG and OUTH are referenced to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH. DAC G Buffered Output Voltage DAC F Buffered Output Voltage Device Sense Ground Input for OUTE and OUTF. In normal operation, OUTE and OUTF are referenced to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF. DAC E Buffered Output Voltage Positive Reference Input for DACs C, D, E, and F Negative Reference Input for DACs C, D, E, and F DAC D Buffered Output Voltage Device Sense Ground Input for OUTC and OUTD. In normal operation, OUTC and OUTD are referenced to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD. DAC C Buffered Output Voltage DAC B Buffered Output Voltage FUNCTION
8
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
_______________Detailed Description
CLR R R OUT 2R 2R 2R 2R 2R 2R
MAX5264
Analog Section
The MAX5264 contains eight 14-bit voltage-output DACs. These DACs are "inverted" R-2R ladder networks that convert 14-bit digital inputs into equivalent analog output voltages, in proportion to the applied reference voltages (Figure 1). The MAX5264 has three positive reference inputs (REF_ _ _ _+) and three negative reference inputs (REF_ _ _ _-). The difference from REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the DAC output span. In addition to the differential reference inputs, the MAX5264 has four analog-ground input pins (DUTGND_ _). When CLR is high (unasserted), the voltage on DUTGND_ _ offsets the DAC output voltage range. If CLR is asserted, the output amplifier is forced to the voltage present on DUTGND_ _.
D0
D12
D13 DUTGND
REF-
REF+
Figure 1. DAC Simplified Circuit
Reference and DUTGND Inputs
All of the MAX5264's reference inputs are buffered with precision amplifiers. This allows the flexibility of using resistive dividers to set the reference voltages. Because of the relatively high multiplying bandwidth of the reference input (188kHz), any signal present on the reference pin within this bandwidth is replicated on the DAC output. The DUTGND pins of the MAX5264 are connected to the negative source resistor (nominally 115k) of the output amplifier. The DUTGND pins are typically connected directly to analog ground. Each of these pins has an input current that varies with the DAC digital code. If the DUTGND pins are driven by external circuitry, budget 200A per DAC for load current.
t1 CS t4 t2 WR t8 t9 A0-A2 t5
t6 D0-D13
t7
Output Buffer Amplifiers
The MAX5264's voltage outputs are internally buffered by precision gain-of-two amplifiers with a typical slew rate of 1V/s. With a full-scale transition at its output, the typical settling time to 1LSB is 22s. This settling time does not significantly vary with capacitive loads less than 10,000pF.
t3 t3 LD
(NOTE 3)
Output Deglitching Circuit
The MAX5264's internal connection from the DAC ladder to the output amplifier contains special deglitch circuitry. This glitch/deglitch circuitry is enabled on the falling edge of LD to remove the glitch from the R-2R DAC. This enables the MAX5264 to exhibit a fraction of the glitch impulse energy of parts without the deglitching circuit.
NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tr = tf = 5ns. 2. MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2. 3. IF LD IS ACTIVATED WHILE WR IS LOW, THEN LD MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH.
Figure 2. Digital Timing Diagram _______________________________________________________________________________________ 9
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and CMOS logic. The MAX5264 interfaces with microprocessors using a data bus at least 13 bits wide. The interface is double buffered, allowing simultaneous updating of all DACs. There are two latches for each DAC (see Functional Diagram): an input latch that receives data from the data bus, and a DAC latch that receives data from the input latch. Address lines A0, A1, and A2 select which DAC's input latch receives data from the data bus as shown in Table 2. Both the input latches and the DAC latches are transparent when CS, WR, and LD are all low. Any change of D0-D13 during this condition appears at the output instantly. Transfer data from the input latches to the DAC latches by asserting the asynchronous LD signal. Each DAC's analog output reflects the data held in its DAC latch. All control inputs are level triggered. Table 3 is an interface truth table. Input Write Cycle Data can be latched or transferred directly to the DAC. CS and WR control the input latch, and LD transfers information from the input latch to the DAC latch. The input latch is transparent when CS and WR are low, and the DAC latch is transparent when LD is low. The address lines (A0, A1, A2) must be valid for the duration that CS and WR are low (Figure 2) to prevent data from being inadvertently written to the wrong DAC. Data is latched within the input latch when either CS or WR is high. Loading the DACs Taking LD high latches data into the DAC latches. If LD is brought low when WR and CS are low, the DAC addressed by A0, A1, and A2 is directly controlled by the data on D0-D13. This allows the MAXIMum digital update rate; however, it is sensitive to any glitches or skew in the input data stream. Asynchronous Clear The MAX5264 has an asynchronous clear pin (CLR) that, when asserted, sets all DAC outputs to the voltage present on their respective DUTGND pins. Deassert CLR to return the DAC output to its previous voltage. Note that CLR does not clear any of the internal digital registers.
Table 2. MAX5264 DAC Addressing
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 FUNCTION DAC A input latch DAC B input latch DAC C input latch DAC D input latch DAC E input latch DAC F input latch DAC G input latch DAC H input latch
Applications Information
Multiplying Operation
The MAX5264 can be used for multiplying applications. Its reference accepts both DC and AC signals. Since the reference inputs are unipolar, multiplying operation is limited to two quadrants. See the graphs in the Typical Operating Characteristics for dynamic performance of the DACs and output buffers.
Table 3. Interface Truth Table
CLR X X X X X 0 LD X X X 0 1 X WR 0 X 1 X X X CS 0 1 X X X X FUNCTION Input register transparent Input register latched Input register latched DAC register transparent DAC register latched Outputs of DACs at DUTGND_ _ Outputs of DACs set to voltage defined by the DAC register, the references, and the corresponding DUTGND_ _
Digital Code and Analog Output Voltage
The MAX5264 uses offset binary coding. A 14-bit two's complement code is converted to a 14-bit offset binary code by adding 213 = 8192.
Output Voltage Range
For typical operation, connect DUTGND to signal ground, VREF+ to +4.5V, and VREF- to -2.0V. Table 4 shows the relationship between digital code and output voltage. The DAC digital code controls each leg of the 14-bit R-2R ladder. A code of 0x0 connects all legs of the ladder to REF-, corresponding to a DAC output voltage (VDAC) equal to REF-. A code of 0x3FFF connects all legs of the ladder to REF+, corresponding to a VDAC approximately equal to REF+.
1
1
X
X
X = Don't care 10
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Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
Table 4. Analog Voltage vs. Digital Code
INPUT CODE 11 1111 1111 1111 10 0000 0000 0000 01 0011 1011 0010 00 0000 0000 0001 00 0000 0000 0000 OUTPUT VOLTAGE (V) +8.999207 +2.500 +610 -3.999207 -4.000
Power Supplies, Grounding, and Bypassing
For optimum performance, use a multilayer PC board with an unbroken analog ground. For normal operation, connect the four DUTGND pins directly to the ground plane. Avoid sharing the connections of these sensitive pins with other ground traces. As with any sensitive data-acquisition system, connect the digital and analog ground planes together at a single point, preferably directly underneath the MAX5264. Avoid routing digital signals underneath the MAX5264 to minimize their coupling into the IC. For normal operation, bypass VDD and VSS with 0.1F ceramic chip capacitors to the analog ground plane. To enhance transient response and capacitive drive capability, add 10F tantalum capacitors in parallel with the ceramic capacitors. Note, however, that the MAX5264 does not require the additional capacitance for stability. Bypass VCC with a 0.1F ceramic chip capacitor to the digital ground plane.
MAX5264
Note: Output voltage is based on REF+ = +4.5V, REF- = -2.0V, and DUTGND = 0.
The output amplifier multiplies VDAC by 2, yielding an output voltage range of 2 REF- to 2 REF+ (Figure 1). Further manipulation of the output voltage span is accomplished by offsetting DUTGND. The output voltage of the MAX5264 is described by the following equation: DATA VOUT = 2(VREF + - VREF - ) + VREF - 14 2 - VOUTGND where DATA is the numeric value of the DAC's binary input code, and DATA ranges from 0 to 16383 (214 - 1). The resolution of the MAX5264, defined as 1LSB, is described by the following equation: LSB = 2(REF+ - REF - ) 214
Power-Supply Sequencing
To guarantee proper operation of the MAX5264, ensure that power is applied to VDD before VSS and VCC. Also ensure that V SS is never more than 300mV above ground. To prevent this situation, connect a Schottky diode between VSS and the analog ground plane, as shown in Figure 3. Do not power up the logic input pins before establishing the supply voltages. If this is not possible and the digital lines can drive more than 10mA, place current-limiting resistors (e.g., 470) in series with the logic pins.
Reference Selection
Because the MAX5264 has precision buffers on its reference inputs, the requirements for interfacing to these inputs are minimal. Select a low-drift, low-noise reference within the recommended REF+ and REF- voltage ranges. The MAX5264 does not require bypass capacitors on its reference inputs. Add capacitors only if the reference voltage source requires them to meet system specifications.
VSS
VSS VSS MAX5264 1N5817
Minimizing Output Glitch
The MAX5264's internal deglitch circuitry is enabled on the falling edge of LD. Therefore, to achieve optimum performance, drive LD low after the inputs are either latched or steady state. This is best accomplished by having the falling edge of LD occur at least 50ns after the rising edge of CS.
GND
SYSTEM GND
Figure 3. Schottky Diode Between VSS and GND ______________________________________________________________________________________ 11
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Driving Capacitive Loads
The MAX5264 typically drives capacitive loads up to 0.01F without a series output resistor. However, whenever driving high capacitive loads, it is prudent to use a 220 series resistor between the MAX5264 output and the capacitive load.
Chip Information
TRANSISTOR COUNT: 13,225 PROCESS: BiCMOS
12
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VDD VSS OUTA
CLR 14 DAC REG A DAC A DATA R REG A 14
D0- D13
14
ANALOG POWER SUPPLY
VCC DAC B OUTB
14 DATA REG B DAC REG B
14
14
GND
DIGITAL POWER SUPPLY DUTGNDAB DAC C OUTC
14 DATA REG C DAC REG C
14
14
14 DAC D DATA REG D DAC REG D
14
14 OUTD
14 DAC E
14
14
DUTGNDCD OUTE
ADDRESS DECODE LOGIC 14 DAC F DAC REG F 14
DATA REG E
DAC REG E
14 DATA REG F
OUTF
A2 14 DAC G OUTG DAC REG G 14 DUTGNDEF
A1 DATA REG G
14
A0
CS 14 DAC H DAC REG H 14 DATA REG H
14
WR
OUTH
LD MAX5264 REFABREFAB+ REFGHREFGH+ REFCDEFREFCDEF+
MAX5264
______________________________________________________________________________________
DUTGNDGH
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE
Functional Diagram
13
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
Package Information
MQFP44.EPS
14
______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
NOTES
______________________________________________________________________________________
15
Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE MAX5264
NOTES
MAXIM cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a MAXIM product. No circuit patent licenses are implied. MAXIM reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________MAXIM Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 MAXIM Integrated Products Printed USA is a registered trademark of MAXIM Integrated Products.

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